A Highly Reliable 2-Bits/Cell Split-Gate Flash Memory Cell With a New Program-Disturbs Immune Array Configuration

A highly reliable 2-bits/cell split-gate flash memory cell in a novel program-disturbs immune array architecture is fabricated and demonstrated. Using a novel metal interconnect technique, a new virtual-ground array architecture is realized to greatly improve program disturbs as compared with conventional and-type configuration. A fully self-aligned process with shallow trench isolation in cell array is also proposed for the first time to fabricate this word-line shared split-gate structure without any lithomisalignment issue. Moreover, the negative charge trap in select gate (SG) oxide during conventional poly-to-poly Fowler-Nordheim tunneling erase operation is found as an important contribution to the cycling degradation for cells with thin SG oxide, and a negative control gate bias erase scheme is then presented to enhance the endurance reliability in this paper. A 250-°C baking experiment (before and after cycling) is performed to explore this cell´s data retention characteristics, proving the free of extrinsic and intrinsic defect. Erase and program characteristics are comparable with conventional split-gate cell as well.