Current-Mode Pipelined ADC for High Resolution Monolithic CCD Processors

Author

Bernal, O. ; Cousineau, M. ; Lescure, M. ; Seat, H.C.

Author_Institution

Lab. d´´Electronique de l´´E.N.S.E.E.I.H.T., Toulouse

Volume

1

fYear

2005

fDate

16-19 May 2005

Firstpage

13

Lastpage

18

Abstract

This paper describes a new differential current memory cell which is based on the Miller effect and an interleaved ADC architecture. As far as the CMC is concerned, it was pointed out that the opamp design is not an issue to achieve high performances. Simulation results show good performances for sampling rates up to 20MS/s (assuming 22ns for both sampling and holding mode) and relatively large current input signals of mnplus200muA. The originality of the proposed interleaved ADC architecture consists in improving the ADC sampling rate with minimum penalty to SNR performances

Keywords

analogue-digital conversion; current-mode circuits; integrated memory circuits; Miller effect; analog-to-digital converters; current-mode pipelined ADC; differential current memory cell; interleaved ADC architecture; monolithic CCD processors; opamp design; operational amplifiers; Analog-digital conversion; CMOS technology; Charge coupled devices; Circuits; Dynamic range; Embedded system; Energy consumption; Linearity; Space technology; Voltage; CCD processors; current memory cell; current pipelined ADC; interleaving; low-power/low-voltage; video AFE;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2005. IMTC 2005. Proceedings of the IEEE

Conference_Location

Ottawa, Ont.

Print_ISBN

0-7803-8879-8

Type

conf

DOI

10.1109/IMTC.2005.1604059

Filename

1604059