Understanding and Enhancing the Performance of Parallel Clockless Transient Waveform Digitizers

Parallel clockless architectures possess advantages compared with traditional serial clocked architectures for digitization of high-speed transient waveforms. In particular, such devices support high sampling rates and are not susceptible to trigger jitter. Additionally, parallel clockless architectures possess systematic errors, epsiv(n) and A(n,y), which can often be calibrated or otherwise corrected. Such calibration results in improved measurement quality, as demonstrated by an LIF experiment. Additional work remains to treat dynamic and other errors