A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver

Author

Ping, Lu ; Yan, Wang ; Lian, Li ; Junyan, Ren

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

Volume

1

fYear

2005

fDate

24-27 Oct. 2005

Firstpage

391

Lastpage

394

Abstract

A frequency synthesizer applied to 10/100 Base-T Ethernet transceiver is described. It can work in 10Mbps or 100Mbps mode adaptively and convert from one mode to another freely. The circuit can meet both requirements of transmitter on rising/falling time and receiver on CDR so that the additional power and area are saved. Under some testing circumstance, G of voltage control oscillator jitter_cycle-cycle is only 22ps with G of reference clock jitter_cycle-cycle 25ps (Herzel and Razavi, 1997). The testing result proves that the frequency synthesizer has good processing stability and rejection to noises. It works well for transmitter and receiver. The circuit is designed with SMIC 0.35μm standard CMOS technology and the power supply is 3.3V.

Keywords

CMOS integrated circuits; frequency synthesizers; local area networks; transceivers; voltage-controlled oscillators; 0.35 micron; 10 Mbit/s; 100 Mbit/s; 22 ps; 3.3 V; CDR; CMOS technology; fast Ethernet transceiver; low-jitter frequency synthesizer; reference clock jitter; voltage control oscillator; CMOS technology; Circuit testing; Clocks; Ethernet networks; Frequency synthesizers; Jitter; Transceivers; Transmitters; Voltage control; Voltage-controlled oscillators; 1230; 1280; Ethernet; clock jitter EEACC: 1205; frequency synthesizer;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611345

Filename

1611345