DocumentCode
453679
Title
A phase-locked loop for receivers of UHF wireless microphone
Author
Huang, Chun-Yueh ; Chao, I-Jeng ; Wang, Hung-Yu
Author_Institution
Inst. of Commun. Eng., National Univ. of Tainan, Taiwan
Volume
1
fYear
2005
fDate
24-27 Oct. 2005
Firstpage
423
Lastpage
426
Abstract
A novel phase-locked loop (PLL) design for the receivers of UHF wireless microphone is presented. The output-frequency range of the proposed circuit is from 800MHz to 1200MHz with 50MHz interval. It can provide nine frequency channels for UHF wireless microphone application. A programmable multi-modulus frequency divider is employed which enables the dividing ratios within 16-24. The proposed PLL circuit is designed based on the TSMC 0.35μm CMOS technology with a 3.3V supply voltage. The feasibility is confirmed with post-layout HSPICE simulations.
Keywords
CMOS integrated circuits; frequency dividers; integrated circuit design; microphones; phase locked loops; radio receivers; 0.35 micron; 3.3 V; 800 to 1200 MHz; CMOS technology; UHF wireless microphone; phase-locked loop; programmable multimodulus frequency divider; receivers; Charge pumps; Circuits; Feedback; Filters; Frequency conversion; Microphones; Phase frequency detector; Phase locked loops; Switches; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611351
Filename
1611351
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