DocumentCode
454313
Title
Efficient Link Capacity and QoS Design for Network-on-Chip
Author
Guz, Zvika ; Walter, Isask´har ; Bolotin, Evgeny ; Cidon, Israel ; Ginosar, Ran ; Kolodny, Avinoam
Author_Institution
Electr. Eng. Dept., Technion, Haifa
Volume
1
fYear
2006
fDate
6-10 March 2006
Firstpage
1
Lastpage
6
Abstract
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under quality-of-service timing constraints. First, we introduce a novel analytical delay model for virtual channeled wormhole networks with non-uniform link capacities that eliminates costly simulations at the inner-loop of the optimization process. Second, we present an efficient capacity allocation algorithm that assigns link capacities such that packet delays requirements for each flow are satisfied. We demonstrate the benefit of capacity allocation for a typical system on chip, where the traffic is heterogeneous and delay requirements may largely vary, in comparison with the standard approach which assumes uniform-capacity links
Keywords
integrated circuit design; integrated circuit modelling; multiprocessor interconnection networks; network-on-chip; quality of service; capacity allocation; delay model; efficient link capacity; network-on-chip based system; packet delays; quality-of-service timing constraints; system on chip; virtual channeled wormhole networks; Analytical models; Costs; Delay; Network-on-a-chip; Process design; Quality of service; Radio access networks; Routing; System-on-a-chip; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location
Munich
Print_ISBN
3-9810801-1-4
Type
conf
DOI
10.1109/DATE.2006.243951
Filename
1656837
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