A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications

Author

Lucas, Amilcar Do Carmo ; Heithecker, Sven ; Rüffer, Peter ; Ernst, Rolf ; Rückert, Holger ; Wischermann, Gerhard ; Gebel, Karin ; Fach, Reinhard ; Huther, Wolfgang ; Eichner, Stefan ; Scheller, Gunter

Author_Institution

Tech. Univ. of Braunschweig

Volume

1

fYear

2006

fDate

6-10 March 2006

Firstpage

1

Lastpage

6

Abstract

This paper presents a multi-board, multi-FPGA hardware/software architecture, for computation intensive, high resolution (2048times2048pixels), real-time (24 frames per second) digital film processing. It is based on Xilinx Virtex-II Pro FPGAs, large SDRAM memories for multiple frame storage and a PCI express communication network. The architecture reaches record performance running a complex noise reduction algorithm including a 2.5 dimensions DWT and a full 16times16 motion estimation at 24 fps requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth. To increase design productivity and yet achieve high clock rates (125MHz), the architecture combines macro component configuration and macro level floorplanning with weak programmability using distributed microcoding. As an example, the core of the bidirectional motion estimation using 2772 CLBs reaching 155 Gop/s (1538 op/pixel) requiring 7 Gbit/s external memory bandwidth was developed in two men-months

Keywords

DRAM chips; computational complexity; field programmable gate arrays; hardware-software codesign; image processing; motion compensation; motion estimation; peripheral interfaces; 125 MHz; 28 Gbit/s; 7 Gbit/s; PCI express communication network; SDRAM memories; Xilinx Virtex-II Pro FPGA; digital film processing; field programmable gate arrays; hardware-software architecture; motion compensation; motion estimation; multiple frame storage; Application software; Bandwidth; Communication networks; Computer architecture; Field programmable gate arrays; Hardware; Motion estimation; Noise reduction; SDRAM; Software architecture; FPGA; digital film; motion-estimation; reconfigurable; stream-based architechture; weak-programming;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings

Conference_Location

Munich

Print_ISBN

3-9810801-1-4

Type

conf

DOI

10.1109/DATE.2006.244085

Filename

1656875