Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion

Functional unit shutdown based on MTCMOS devices is effective for leakage reduction in aggressively scaled technologies. However, the applicability of MTCMOS-based shutdown in a synthesis-based design flow poses the challenge of interfacing logic blocks in shutdown mode with active units: The outputs of inactive gates can float at intermediate voltages, causing very large short-circuit currents in the active gates they drive. In this paper, we propose two novel low-overhead elementary cells that fully address this issue. These cells can be added to any synthesis library, and they can be inserted into a netlist at the boundary between shutdown and active regions. Our results show that: (i) our cells solve the interfacing problem with minimum overhead; and (ii) a non-intrusive design flow enhancement is sufficient to automatically insert interface cells in post-synthesis netlists