An Low Complexity Hardware Implementation of MIMO Detector with Application to WLAN

Author

Yoon, Chanho ; Choi, Eunyoung ; Son, Jungbo ; Lee, Sok-Kyu ; Jeon, Taehyun

Author_Institution

Next Generation Wireless LAN Res. Team, Electron. & Telecommun. Res. Inst., Daejeon

Volume

5

fYear

2006

fDate

7-10 May 2006

Firstpage

2271

Lastpage

2275

Abstract

In this paper, we describe a FPGA implementation of MIMO detector for future wireless communication system with application to wireless LAN, targeted for upcoming 802.11n standard. The MIMO detector assumes 2 transmit and 3 receive antennas. In soft-output demapper, we apply channel state information which effectively weights reliability information to soft-decision output bits for enhanced link-level performance. The implementation complexity is significantly reduced by avoiding repeated pseudo-inverse calculation for interference cancellation of every received symbol vector. Furthermore, the overall processing time and fabrication area it takes can be significantly reduced by applying bit reduction technique

Keywords

MIMO systems; antenna arrays; detector circuits; field programmable gate arrays; interference suppression; receiving antennas; transmitting antennas; wireless LAN; 802.11n standard; FPGA; MIMO detector; WLAN; bit reduction technique; future wireless communication system; interference cancellation; low complexity hardware implementation; multiple input multiple output; soft-output demapper; wireless local area network; Channel state information; Communication standards; Detectors; Field programmable gate arrays; Hardware; Interference cancellation; MIMO; Receiving antennas; Wireless LAN; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Vehicular Technology Conference, 2006. VTC 2006-Spring. IEEE 63rd

Conference_Location

Melbourne, Vic.

ISSN

1550-2252

Print_ISBN

0-7803-9391-0

Electronic_ISBN

1550-2252

Type

conf

DOI

10.1109/VETECS.2006.1683261

Filename

1683261