CMOS Small-Signal and Thermal Noise Modeling at High Frequencies

In this paper, the behavior of radio frequency (RF) CMOS noise up to 24 GHz is analyzed and verified with measurements over a wide range of bias voltages and channel lengths. For the first time, approaches for excess noise factor modeling are validated versus measurements. Furthermore, important RF CMOS figures of merit are examined over many CMOS generations. With the scaling of CMOS technology, optimum RF performance is shown to be shifted from higher moderate toward lower moderate inversion, providing important guidelines for RFIC design. The results are validated with the charge-based EKV3 compact model, which considers short-channel effects such as channel length modulation, velocity saturation, and carrier heating.