Title :
Application of DDR Controller for High-speed Data Acquisition Board
Author :
Zhou, Zude ; Cheng, Songlin ; Liu, Quan
Author_Institution :
Sch. of Inf. Eng., Wuhan Univ. of Technol.
fDate :
Aug. 30 2006-Sept. 1 2006
Abstract :
DDR SDRAM (double data rate synchronously dynamic RAM) controller is discussed in this paper. The principle and commands of FPGA-based DDR SDRAM controller are detailed. The R/W control of DDR SDRAM is realized through Verilog HDL, and this controller is applied into 400 MHz single channel high-speed, high-precision and large-capacity data acquisition board
Keywords :
DRAM chips; control system synthesis; data acquisition; field programmable gate arrays; hardware description languages; logic design; FPGA-based DDR SDRAM controller; Verilog HDL; double data rate synchronously dynamic RAM controller; high-speed data acquisition board; Bridge circuits; Clocks; Communication system control; DRAM chips; Data acquisition; Field programmable gate arrays; Hardware design languages; Random access memory; SDRAM; Throughput;
Conference_Titel :
Innovative Computing, Information and Control, 2006. ICICIC '06. First International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7695-2616-0
DOI :
10.1109/ICICIC.2006.237
