• DocumentCode
    456817
  • Title

    Parity-based on-line detection for a bit-parallel systolic dual-basis multiplier over GF(2/sup m/)

  • fYear
    2006
  • fDate
    21-24 May 2006
  • Abstract
    The finite field is widely used in error-correcting codes and cryptography. Among its important arithmetic operations, multiplication is identified as the most important and complicated. Therefore, a multiplier with concurrent error detection ability is elegantly needed. In this paper, a concurrent error detection scheme is presented for bit-parallel systolic dual basis multiplier over GF(2m). The proposed multiplier takes only one extra clock cycle while traditional multipliers using XOR trees consume at least extra XOR gate delays in GF(2m) fields. Our analysis shows that all single stuck-at faults can be detected concurrently
  • Keywords
    Galois fields; delays; error correction codes; error detection; logic gates; logic testing; multiplying circuits; trees (mathematics); XOR gate; bit-parallel systolic dual-basis multiplier; error correcting codes; error detection; stuck-at faults; Delay effects; Error analysis; Error correction coding; Galois fields; Logic circuit testing; Multiplying circuits; Trees (graphs);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
  • Conference_Location
    Island of Kos
  • Print_ISBN
    0-7803-9389-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2006.1692702
  • Filename
    1692702