Fabric on a Chip: Towards Consolidating Packet Switching Functions on Silicon

To resolve the high memory bandwidth requirements presented by output-queued switches, several parallel shared-memory architectures have been previously proposed. In this paper, our goal is to extend existing shared-memory architecture results while introducing the notion of Fabric on a Chip (FoC). In taking advantage of recent advancements in integrated circuit technologies, FoC aims to facilitate the consolidation of as many packet switching functions as possible on a single chip. Accordingly, this paper focuses a novel pipelined memory management algorithm which plays a key role in the context of on-chip output-queued switch emulation. We discuss in detail the fundamental properties of the proposed scheme, along with FPGA-based implementation results that illustrate its scalability and performance attributes.