Implementation of Constrained Partitioned Broadband Antenna Array Processor Using the DFT Method

Constrained partitioned processor is an alternative structure to an element space broadband antenna array processor using a tapped delay line filter with N taps. It consists of a fixed main beam to receive the signal from the look direction and a set of auxiliary beams for an L element array. The weighted sum of these beams is used to minimize the noise in the main beam requiring the inverse of a matrix of the order of LN times LN. This paper presents a method to estimate the weights of the auxiliary beams in parallel requiring the inverse of a matrix of the order of L times L and thus reducing the computational cost substantially. It is shown that the proposed method is more robust to look direction errors compared to the original structure