Impact of non ideal signal transfer of on-chip source-follower JFET on Silicon Drift Detector noise performance

Silicon drift detectors (SDD) for high-resolution X-ray spectroscopy feature an n-channel JFET in source follower configuration directly integrated on the detector chip. This stage has the key role to buffer the small anode capacitance, on which the signal charge is converted, from the (larger) interconnection strays and input capacitance of the external voltage preamplifier. However the maximum voltage gain of on-detector JFETs (i.e. the product of its transconductance and output resistance) is typically limited to about 10 or even less due to the constraints of detector-grade technology on high-resistivity silicon. In this situation the signal transfer of the JFET source-follower stage departs from the ideal behavior and, as the gate-source capacitance of the JFET is not perfectly bootstrapped, the input and output impedances influence each other. Such effect leads to a degradation of the noise performance especially in the case of very small anode capacitance and must be taken into account to optimize the design of SDD with anode capacitance of few tens of femtoFarad and to get a realistic estimate of the ultimate achievable energy resolution scaling the size of the readout section.