FPGA Implementation of a GLST-MIMO System

Author

Higashi, Kota ; Nagao, Yuhei ; Kurosaki, Masayuki ; Ochi, Hiroshi

Author_Institution

Dept. of Comput. Sci. & Electron. Eng., Kyushu Inst. of Technol., Fukuoka

Volume

1

fYear

2007

fDate

12-14 Feb. 2007

Firstpage

282

Lastpage

285

Abstract

This paper presents an FPGA implementation of a GLST-MIMO detector for GLST-MIMO wireless communication systems. The proposed system provides a maximum of 600 Mbps using the 80 MHz baseband bandwidth of the 4times2 MIMO scheme. The GLST-MIMO detector adopts a detection algorithm to low-computational complexity, as low as O(M_Tx ²) = O(4²) (M_Tx : number of transmit antennas) per symbol interval, by using the orthogonality of the channel matrix. The GLST-MIMO detector architecture meets the timing constraints of real-time processing.

Keywords

MIMO communication; computational complexity; field programmable gate arrays; matrix algebra; signal detection; 80 MHz; FPGA implementation; GLST-MIMO detector; GLST-MIMO wireless communication systems; channel matrix; computational complexity; group layered space time; Bandwidth; Baseband; Block codes; Computational complexity; Detection algorithms; Detectors; Field programmable gate arrays; MIMO; Space technology; Wireless communication; FPGA implementation; group layered space-time-MIMO system; layered space-time; space-time block coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Communication Technology, The 9th International Conference on

Conference_Location

Gangwon-Do

ISSN

1738-9445

Print_ISBN

978-89-5519-131-8

Type

conf

DOI

10.1109/ICACT.2007.358356

Filename

4195135