A Study on Impact of Leakage Current on Dynamic Power

Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now become comparable to the switching current. Traditionally, dynamic power and leakage power are computed separately. Dynamic power computation does not include leakage from non-switching nodes. In this paper, we show that in upcoming 45nm technology, leakage from non-switching nodes can account for as much as 38% of total dynamic current. Hence leakage from non-switching nodes can not be neglected during dynamic power computation. To facilitate this study on large benchmark circuits on which spice level simulation is impractical, we created a compact simulation model for modeling various pattern dependent leakage currents to allow leakage computation at gate level. Using a simulation based experiment we compare leakage and switching currents on ISCAS-85 benchmark circuits. The experiments are based on Berkeley predictive technology model for 45nm technology. The results firmly establish the need to consider leakage from non-switching nodes during dynamic power computation.