Efficient Color Space Conversion using Custom Instruction in a RISC Processor

Author

Bilal, Muhammad ; Masud, Shahid

Author_Institution

Dept. of Comput. Sci. & Eng., Lahore Univ. of Manage. Sci.

fYear

2007

fDate

27-30 May 2007

Firstpage

1109

Lastpage

1112

Abstract

A new architecture for color space conversion in RGB to YCbCr domain has been proposed. The architecture exploits the similarity in bit-planes of a natural image to bring the algorithmic efficiency of distributed arithmetic (DA) approach close to that of a full multiplier design. Modifications have been carried out in DA to further reduce the computational complexity by a factor of two for most natural images. The color space conversion architecture has been incorporated in OR1200 open source IP processor core to provide custom instruction. Simulation and synthesis results on Xilinx FPGA are provided.

Keywords

distributed arithmetic; field programmable gate arrays; image colour analysis; microprocessor chips; reduced instruction set computing; FPGA; IP processor core; RISC processor; YCbCr domain; color space conversion; computational complexity; custom instruction; distributed arithmetic approach; multiplier design; natural images; Application software; Arithmetic; Chromium; Clocks; Color; Computer architecture; Field programmable gate arrays; Hardware; Image converters; Reduced instruction set computing; Color space; Distributed Arithmetic; Instruction Set Extension; RISC processor; bit-planes;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378204

Filename

4252833