Address Code Optimization Exploiting Code Scheduling in DSP Applications

Exploitation of address generation units (AGUs) which are typically provided by digital signal processors (DSPs) plays an important role in DSP code generation for embedded processors. In this paper, a novel address code optimization technique for DSP code generation which integrates code scheduling has been presented. Specifically, we develop a probability based quality estimation scheme to search for the globally optimal address assignment. The proposed technique is general enough to handle the situations with commutative-input operands, loops, and conditional branches. The experimental results with DSP benchmark programs show 14%-54% improvement in terms of the number of nonzero-cost address instructions