Current-Mode Phase-Locked Loops with Low Supply Voltage Sensitivity

This paper presents the architecture and design of current-mode phase-locked loops. The proposed current-mode PLLs differ from conventional voltage-mode PLLs by replacing their RC loop filter with a RL loop filter, eliminating the need for area-consuming capacitors. The large inductance of the current-mode loop filter is obtained from CMOS active inductors, taking the advantage of their large and tunable inductance and small silicon area. Replica-biasing techniques are used to minimize the effect of supply voltage fluctuation on the performance of active inductors. Implemented in TSMC-0.18mum CMOS technology, the simulation results of a 2.4GHz current-mode PLL demonstrate that the PLL has the lock time of 300ns approximately, dc power consumption 7.76mW, and phase noise of -110dBc at 1MHz frequency offset.