DocumentCode
464989
Title
Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology
Author
Roubadia, Régis ; Ajram, Sami ; Cathébras, Guy
Author_Institution
ATMEL, Rousset
fYear
2007
fDate
27-30 May 2007
Firstpage
2490
Lastpage
2493
Abstract
This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240 MHz frequency range have been realized in 0.18mum standard CMOS process, with a 1.8 V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240 MHz without increasing the power consumption, which is 2.4 mW at 240 MHz.
Keywords
CMOS integrated circuits; phase locked loops; voltage-controlled oscillators; 0.18 micron; 1.8 V; 2.4 mW; 80 to 240 MHz; multiphase direct realignment; multiphase realigned PLL; phase locked loop; standard CMOS process; submicronic CMOS technology; voltage controlled oscillator; Bandwidth; CMOS technology; Clocks; Energy consumption; Frequency; Jitter; Phase locked loops; Phase noise; Power supplies; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378744
Filename
4253182
Link To Document