A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits

In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interference in mixed-signal environments cause designers to be less reliant on optimization based solely on schematic models. Performance can be further improved at the physical design level. Hierarchical optimization schemes are used to manage the complexity in the analog circuit design process. In this paper, we present a novel performance-driven compaction optimization algorithm that optimizes the placement of circuit blocks and guard bands for analog circuits. Parasitic effects are minimized under symmetry, matching and displacement constraints derived from the customized layout topology.