Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing

This paper presents a solution to the multi-frequency heterogeneous SoC test integration and reuse, which is considered the major hurdle of SoC manufacturing capability, and thus is the key component of SoC test automation. A hybrid system level test framework is designed and optimized to tackle heterogeneous test environment with the combination of BIST and the external test. Several interdependent design items including test access mechanism design, bandwidth matching, multi-frequency interface configuration, and test scheduling under tight power and pin count limitation, are well studies and incorporated into the test framework. The trade-off between test time, test power and bandwidth is well balanced to achieve the minimum test cost in terms of test time and test interface. The simulation study shows the promising results of the proposed floor-ceiling packing approach.