Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations

This paper is a case study of dual-14 configurations of an SRAM cell considering process-induced V_t variations. Dual threshold voltage assignment is an effective technique to reduce leakage power without any area overhead, however as we will show the quality of a dual-threshold assignment highly varies due to process parameter variations in deca-nanometer designs of today. We analyze and compare the effects of process-induced V_t variations in 11 dominant dual-14 cell configurations. Under process variations each configuration is evaluated based on the probability density functions (pdfs) of its read delay, leakage current and read stability, accurately obtained using Monte Carlo simulations for 90nm generic process design kit of Cadence. Comparison of different cell configurations is based on evaluating these pdfs at points corresponding to a desired yield. We show that the choice of the best dual-V_t configuration varies depending on a given yield, and show tradeoff plots between read delay, leakage and read margin of different configurations under variations.