A Low-cost and High-performance SoC Design for OMA DRM2 Applications

Author

Gu, Yehua ; Zeng, Xiaoyang ; Han, Jun ; Zhao, Jia

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai

fYear

2007

fDate

27-30 May 2007

Firstpage

3510

Lastpage

3513

Abstract

A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several design aspects, which include an embedded 32-bits RISC CPU and AMBAtrade bus system, a DRM Agent accelerator, a high-performance TRNG, several interfaces and reasonable hardware/software partition, making it very efficient for the OMA DRM 2 application. Based on SMIC 0.25mum standard CMOS technology, the proposed SoC platform can work under the frequency of about 76MHz, and the core circuit is 112k gates, making it suitable for low-cost design. Besides, memory protection unit is added to enhance the security. Therefore, the proposed SoC platform has a fine potential in application.

Keywords

CMOS integrated circuits; integrated circuit design; mobile handsets; system-on-chip; 0.25 micron; 76 MHz; AMBAtrade bus system; DRM agent accelerator; OMA DRM2; RISC CPU; SMIC; SoC design; low cost design; mobile phones; Accelerated aging; Application software; CMOS memory circuits; CMOS technology; Embedded software; Field programmable gate arrays; Frequency; Hardware; Mobile handsets; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378439

Filename

4253437