Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs

This paper highlights the problem of test-bus power reduction in system-on-chip testing. It has been shown that while the cores are fitted with IEEE 1500 wrapper, transitions occurring within test bus and bypass registers can be comparable to those in the scan-chain. Unlike bus encoding the proposed solution does not use any extra hardware and neither affects the compression ratio, nor test application time. Experimental results on ISCAS89 benchmark circuits show up to 87% saving of transitions occurring in test bus in a Huffman coding based test data compression mechanism. A trade-off mechanism has also been shown between compression and test-bus power consumption.