Capacitively-Biased Floating-Gate CMOS: a New Logic Family

Given a particular digital logic path and a desired operating frequency there exists an optimal trade off of dynamic, static, and short-circuit power dissipation. Techniques like DVS and variable thresholds exist to bring paths closer to this optimum, but intrinsic complications limit how close they can get. We present capacitively-biased, floating-gate CMOS (FG-CMOS) as a new, and intrinsically more efficient, logic family that removes many of these complications as well as giving rise to new dimensions of design and run time optimizations previously unattainable. Simulations are performed to explore the energy per cycle versus cycle time of arbitrary digital logic paths, and show FG-CMOS capable of running atleast 12% faster at the same power, or at 36% less power at the same speed, or when 20% slack is introduced 65% less power than regular CMOS or 37% less power than DVS CMOS. Devices were fabricated to show functionality, explore area ramifications, and to validate simulation.