High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator

This paper presents the design of a 12 Gbps multi-lane 2³¹ - 1 pseudo-random binary sequence (PRBS) generator in 0.18 mum TSMC process. The design incorporates a traditional CMOS latch optimized to operate at frequencies close to the f_t of the process. In order to operate at frequencies higher than the limit imposed by the f_t of the PMOS devices, the PRBS uses current-mode logic (CML) multiplexers (MUX) with modified active inductors, resulting in an improved large-signal behavior. As the architecture of choice for the PRBS generator, we chose to generate four sub-sequences at 3 Gbps and multiplex them up to obtain a 12 Gbps data stream. Furthermore, we multiplexed delayed versions of the 3 Gbps sub-sequences to obtain multiple non-correlated versions of the 2³¹ - 1 pseudo-random sequence. A prototype was implemented in 0.18 mum TSMC process. The high-speed CML MUX consumes 4 mA off a 1.8 V power supply, while the CMOS latch clocked at 1.5 GHz with an activity factor of 100% consumes 1 mA. The CMOS core consumes 340 mA and the CML circuitry consumes 32 mA per lane.