Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering

The increase in the circuit complexity of a wide-issue processor with its pipeline width is one of the primary concerns of the processor designers. In the conventional design, hardware in the processor core is laid out to handle multiple instructions with two-source operands in each pipeline stage. However, analysis of characteristics of the SPEC2000 integer programs reveals that 74% of instructions require one or less source register operands, and FP programs on average have 60% integer instructions three-fourth of which require one or less source register operands. To alleviate the complexity issues we propose split pipeline architecture, a novel technique to distinguish and process integer instructions based on their source operand requirements. This leads to a capability of processing instructions at a higher clock rate and at almost the same IPC, as compared to a conventional processor.