• DocumentCode
    465255
  • Title

    TROY: Track Router with Yield-driven Wire Planning

  • Author

    Cho, Minski ; Xiang, Hua ; Puri, Ruchir ; Pan, David Z.

  • Author_Institution
    Univ. of Texas at Austin, Austin
  • fYear
    2007
  • fDate
    4-8 June 2007
  • Firstpage
    55
  • Lastpage
    58
  • Abstract
    In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed from critical area analysis and defect size distribution strongly depends on wire ordering, sizing, and spacing, track routing plays a key role in effective wire planning for yield optimization. TROY formulates wire ordering into a preference-aware minimum Hamiltonian path problem. For simultaneous wire sizing and spacing optimization, TROY solves it optimally by formulating the problems into a second order conic programming (SOCP). Experimental results show that TROY can reduce the random-defect yield loss by 18% on average without any overhead in wirelength, compared with the widely used greedy approach.
  • Keywords
    VLSI; integrated circuit layout; integrated circuit yield; network routing; critical area analysis; defect size distribution; failure probability; random defects; second order conic programming; track router; wire ordering; wire sizing; wire spacing; yield optimization; yield-driven wire planning; Algorithm design and analysis; Distributed computing; Failure analysis; Hardware; Integrated circuit interconnections; Integrated circuit manufacture; Integrated circuit yield; Routing; Very large scale integration; Wire; Algorithms; Design; Manufacturability; Performance; Track Routing; VLSI; Yield;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
  • Conference_Location
    San Diego, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-59593-627-1
  • Type

    conf

  • Filename
    4261143