DocumentCode
465304
Title
Single-Event-Upset (SEU) Awareness in FPGA Routing
Author
Golshan, S. ; Bozorgzadeh, E.
Author_Institution
Univ. of California, Irvine
fYear
2007
fDate
4-8 June 2007
Firstpage
330
Lastpage
333
Abstract
The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with comparable delay, hi addition, in asymmetric SRAM FPGA using our router average FIT (failure-in-time) rate is reduced by 36%.
Keywords
SRAM chips; delays; failure analysis; fault diagnosis; field programmable gate arrays; integrated circuit design; network routing; FPGA routing; asymmetric SRAM FPGA; bridging faults; circuit design; configuration bits; delay; failure-in-time rate; routing architecture; single-event-upset awareness; Algorithm design and analysis; Circuit faults; Computer architecture; Computer science; Field programmable gate arrays; Permission; Random access memory; Routing; Switches; Testing; Algorithms; Design; Reliability; SRAM-based FPGA; Theory; routing; single-event-upset; soft error;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location
San Diego, CA
ISSN
0738-100X
Print_ISBN
978-1-59593-627-1
Type
conf
Filename
4261200
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