• DocumentCode
    465331
  • Title

    Analog Placement Based on Novel Symmetry-Island Formulation

  • Author

    Lin, Po-Hung ; Lin, Shyh-Chang

  • Author_Institution
    Nat. Taiwan Univ., Taipei
  • fYear
    2007
  • fDate
    4-8 June 2007
  • Firstpage
    465
  • Lastpage
    470
  • Abstract
    In this paper, we present the first amortized linear-time packing algorithm for the placement with symmetry constraints. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible B*-trees (ASF-B*-trees) to directly model the placement of a symmetry island. Unlike the previous works that can handle only ID symmetry constraints, our ASF-B*-tree is the first in the literature to additionally consider 2D symmetry. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and non-symmetry modules. Unlike the previous works, our approach can guarantee the close proximity of symmetry modules and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*- tree or an HB*-tree is the same as that for a plain B*-tree (only amortized linear) and much faster than previous works which need at least loglinear time. Experimental results show that our approach achieves the best published quality and runtime efficiency for analog placement.
  • Keywords
    analogue integrated circuits; computational complexity; group theory; integrated circuit layout; trees (mathematics); amortized linear-time packing algorithm; analog layout design; analog placement; automatically symmetric-feasible B*-trees; symmetry constraints; symmetry group; symmetry-island formulation; Algorithm design and analysis; Analog integrated circuits; Binary trees; Integrated circuit layout; Research and development; Routing; Runtime; Space exploration; Thermal degradation; Voltage; Algorithms; Analog placement; Design; floorplanning; symmetry;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
  • Conference_Location
    San Diego, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-59593-627-1
  • Type

    conf

  • Filename
    4261229