Nanometer Device Scaling in Subthreshold Circuits

Subthreshold circuit design is a strong candidate for use in future low power applications. It is not clear, however, that device scaling to 45 nm and beyond will be beneficial in subthreshold circuits. We investigate the implications of device scaling on subthreshold circuits and find that the slow scaling of gate oxide thickness leads to a 60 % reduction in I_on/I_off between the 90 nm and 32 nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in sub-V_th circuits.