DocumentCode
465379
Title
Thousand Core ChipsA Technology Perspective
Author
Borkar, Shekhar
Author_Institution
Intel Corp., Hillsboro
fYear
2007
fDate
4-8 June 2007
Firstpage
746
Lastpage
749
Abstract
This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute performance in an affordable power envelope. We discuss fine grain power management, memory bandwidth, on die networks, and system resiliency for the many-core system.
Keywords
transistors; die networks; fine grain power management; many-core architecture; memory bandwidth; system resiliency; transistor; CMOS logic circuits; CMOS technology; Computer architecture; Logic arrays; Logic design; Microarchitecture; Multimedia systems; Permission; Power system reliability; Transistors; CMOS; Design; Memory; Performance; Power; Reliability; Variability;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location
San Diego, CA
ISSN
0738-100X
Print_ISBN
978-1-59593-627-1
Type
conf
Filename
4261282
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