• DocumentCode
    465387
  • Title

    Program Mapping onto Network Processors by Recursive Bipartitioning and Refining

  • Author

    Yu, Jia ; Yao, Jingnan ; Bhuyan, Laxmi ; Yang, Jun

  • Author_Institution
    Univ. of California Riverside, Riverside
  • fYear
    2007
  • fDate
    4-8 June 2007
  • Firstpage
    805
  • Lastpage
    810
  • Abstract
    Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network application domains. A remarkable difference with general multiprocessor task scheduling is that NPs are often programmed into a hybrid parallel and pipeline topology. In this paper, we introduce a multilevel balancing and refining algorithm for NP program mapping. We use a divide- and-conquer approach to recursively bipartition the task graph into disjoint subdomains. At each level of bipartition, the processing resources will be co-allocated so that an estimation of throughput can be derived. The bipartition continues until the code of the tasks can be fit into the instruction memory of processing elements. Then the algorithm iteratively refines the solution by migrating tasks from the bottleneck stage to other stages. The performance of our scheme is evaluated with a suite of NP benchmarks using SUIF/Machine SUIF compiler and Intel IXA Architecture Tool. The throughput improvement is significant: average throughput is increased by 20%, and the maximum is 108%.
  • Keywords
    computational complexity; divide and conquer methods; optimisation; pipeline processing; processor scheduling; Intel IXA Architecture Tool; SUIF/Machine SUIF compiler; divide- and-conquer approach; load balanced pipeline; multilevel balancing; network processors; program mapping; recursive bipartitioning; refining algorithm; Delay; Iterative algorithms; Logic; Network topology; Permission; Pipelines; Processor scheduling; Routing; Throughput; Transcoding; Algorithms; Network Processors; Performance; Program Mapping;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
  • Conference_Location
    San Diego, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-59593-627-1
  • Type

    conf

  • Filename
    4261294