Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation

Fast and accurate power analysis is a critical requirement for designing power-efficient system-on-chips (SoCs). Current system-level power analysis tools are incapable of generating power estimates under real-life workloads within an acceptable amount of time, even for moderately complex SoCs. Our work addresses this problem by borrowing on emulation, which is a widely used technique to accelerate functional verification. Unfortunately, hardware emulation of all the necessary functions for full SoC power analysis is likely to be infeasible for most systems, due to constraints on emulation capacity, and the lack of emulation-ready, synthesizable models for some SoC components early in the design process. This paper describes hybrid power estimation, an approach to accelerating SoC power analysis by emulating the functional and power models of a subset of SoC components on an FPGA platform (even a low-cost, off-the-shelf FGPA board). We describe the hardware and software components of the framework, and propose techniques to overcome the challenges posed by limited host-board communication bandwidth. We have implemented a hybrid power estimation framework using a Xilinx Virtex-II Pro emulation platform and software extensions to an HDL simulator, to conduct power analysis of a video decoder SoC. The results indicate 65-332X gains in analysis efficiency over simulation-based power estimation, with no loss in accuracy. Further, we show that the increase in FPGA resource requirements for hybrid power estimation over pure functional emulation are modest.