Digital Channelized Wide Band Receiver Implemented with a Systolic Array of Multi-Rate FIR Filters

A new systolic array digital channelized wide band receiver (DCWBR) architecture is presented, which eliminates the requirement for demultiplexing and FFT subsystems associated with a conventional DCWBR. The regular systolic array structure of pipelined multi-rate FIR filters in the new architecture presents an opportunity for increased clock frequencies and wider band widths compared to the conventional architecture. A parallel systolic array DCWBR architecture is also presented, which facilitates increased resolution and improved signal arbitration. A FIR filter element of the systolic array has been implemented in 0.13 mum CMOS technology for estimating hardware and power requirements for the new DCWBR architecture.