Wave-Pipelining the Global Interconnect to Reduce the Associated Delays

The majority of digital circuits/systems primarily use synchronous clocking methodology. With clock distribution networks dissipating ever more power and the wire delays expected to become dominant, there has been increased activity to provide alternative solutions. This paper explores some potential methods for reducing global interconnect delays and improving throughput between communicating modules. Analysis of the classical repeater insertion is performed and a wave-pipelined repeater insertion scheme that addresses some shortfalls of the classical repeater insertion is proposed. An extension of the wave-pipelined repeater insertion scheme is presented and results show that its data retention capability offers reliable communication between any number of computing elements. The design of the communication channel is based on the assumption that the computing elements employ synchronous clocking while the communication channels are driven by locally generated clocks. Locally generating clocks along the communication channel avoids the clock distribution complexities and offers an ability to stop and start data transfer along the channel without the need for elaborate clock gating circuitry. Furthermore, no additional clock cycles are required to flush the pipe in the event of stalls. The circuitry that generates local clocks increases area and power, but shows significant performance advantages, particularly in providing a seamless interface between communicating modules running at different clock frequencies. Simulation results of the distributed FIFO communication channel in a modest 180 nm technology show locally generated clocks running at 2.22GHz with the memory buffers placed 2 mm apart.