Clock Skew Reduction by Link-region Technique

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. Therefore, it is very important to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length. In this paper, an efficient bounded clock skew routing method is described in an H-tree network, which generalizes the well-known bounded skew tree method by allowing loops between clock regions.