• DocumentCode
    465478
  • Title

    Design of a Digital Architecture for Real-Time Video, Enhancement Based on Illuminance-Reflectance Model

  • Author

    Ngo, Hau T. ; Zhang, Ming Z. ; Tao, Li ; Asari, Vijayan K.

  • Author_Institution
    Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA 23529. hngox001@odu.edu
  • Volume
    1
  • fYear
    2006
  • fDate
    6-9 Aug. 2006
  • Firstpage
    286
  • Lastpage
    290
  • Abstract
    A design of a high performance digital architecture for a nonlinear image enhancement technique is presented in this paper. The image enhancement is based on illuminance-reflectance model which improves the visual quality of digital images and video captured under insufficient or non-uniform lighting conditions [1]. Systolic, pipelined and parallel design techniques are utilized effectively in the proposed FPGA-based architectural design to achieve real-time performance. Estimation and folding techniques are used in the hardware algorithmic design to achieve faster, simpler and more efficient architecture. The video enhancement system is implemented using Xilinx´s multimedia development board that contains a VirtexII-X2000 FPGA and it is capable of processing approximately 66 Mega-pixels (Mpixels) per second.
  • Keywords
    Algorithm design and analysis; Computer architecture; Digital signal processing; Field programmable gate arrays; Image coding; Image enhancement; Parallel processing; Reflectivity; Signal processing algorithms; Streaming media;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
  • Conference_Location
    San Juan, PR
  • ISSN
    1548-3746
  • Print_ISBN
    1-4244-0172-0
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2006.382053
  • Filename
    4267130