• DocumentCode
    465513
  • Title

    Implementation of NEDA-based DCT architecture using even-odd decomposition of the 8 Ã\x97 8 DCT matrix

  • Author

    Chidanandan, Archana ; Moder, Joseph ; Bayoumi, Magdy

  • Author_Institution
    Computer Science and Software Engg., Rose-Hulman Institute of Technology, Terre Haute, Indiana 47803. Email: chidanan@rose-hulman.edu
  • Volume
    1
  • fYear
    2006
  • fDate
    6-9 Aug. 2006
  • Firstpage
    600
  • Lastpage
    603
  • Abstract
    New Distributed Arithmetic has been been applied to the 1-D DCT to produce a low power, high throughput architecture. In previous work, we applied NEDA to the even-odd decomposition matrices of the 8 × 8 forward and inverse DCT. With the proposed approach, the number of adders required for the adder array for the forward DCT and the inverse DCT is fewer than required if NEDA is applied directly to the 8 × 8 DCT and IDCT matrices. This reduction results in few adders needed, without decreasing the throughput. Also, for the inverse DCT, the number of adder stages is reduced, resulting in faster decoding. In this paper, we present the results of the implementation for the forward DCT using 4:2 compressor trees where needed to decrease the delay and show the results obtained from synthesizing the design in 0.18¿ technology using Cadence BuildGates.
  • Keywords
    Computer architecture; Computer science; Decoding; Delay; Digital arithmetic; Discrete cosine transforms; Distributed computing; Matrix decomposition; Software; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
  • Conference_Location
    San Juan, PR
  • ISSN
    1548-3746
  • Print_ISBN
    1-4244-0172-0
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2006.382134
  • Filename
    4267211