Improved Design of Low-Power Register File Using P-type Adiabatic Line Drivers

A register file is one of the most power-consuming blocks in microprocessors because it contains large capacitances on bit lines, word lines, address lines, and storage-cell array, and is frequently accessed. This paper presents a novel low-power register file that is realized entirely based on adiabatic logic. The proposed register file consists of a storage-cell array, address decoders, read/write control circuits, sense amplifiers, and read/write drivers. An N-type dual transmission gate adiabatic logic (N-DTGAL) is used to drive read/write bit lines and read word lines with large capacitances. A P-type dual transmission gate adiabatic logic (P-DTGAL) that is complementary to the N-DTGAL is used to drive write word lines and power the storage cells, so that energy of the storage cells can be well recovered before new values are written. HSPICE simulations indicate that the proposed register file achieves considerable energy savings over similar implementations.