• DocumentCode
    46644
  • Title

    A Novel Grid Synchronization PLL Method Based on Adaptive Low-Pass Notch Filter for Grid-Connected PCS

  • Author

    Kyoung-Jun Lee ; Jong-Pil Lee ; Dongsul Shin ; Dong-Wook Yoo ; Hee-Je Kim

  • Author_Institution
    Dept. of Electr. Eng., Pusan Nat. Univ., Busan, South Korea
  • Volume
    61
  • Issue
    1
  • fYear
    2014
  • fDate
    Jan. 2014
  • Firstpage
    292
  • Lastpage
    301
  • Abstract
    The amount of distributed energy resources (DERs) has increased constantly worldwide. The power ratings of DERs have become considerably high, as required by the new grid code requirement. To follow the grid code and optimize the function of grid-connected inverters based on DERs, a phase-locked loop (PLL) is essential for detecting the grid phase angle accurately when the grid voltage is polluted by harmonics and imbalance. This paper proposes a novel low-pass notch filter PLL (LPN-PLL) control strategy to synchronize with the true phase angle of the grid instead of using a conventional synchronous reference frame PLL (SRF-PLL), which requires a d-q-axis transformation of three-phase voltage and a proportional-integral controller. The proposed LPN-PLL is an upgraded version of the PLL method using the fast Fourier transform concept (FFT-PLL) which is robust to the harmonics and imbalance of the grid voltage. The proposed PLL algorithm was compared with conventional SRF-PLL and FFT-PLL and was implemented digitally using a digital signal processor TMS320F28335. A 10-kW three-phase grid-connected inverter was set, and a verification experiment was performed, showing the high performance and robustness of the proposal under low-voltage ride-through operation.
  • Keywords
    PI control; adaptive filters; digital signal processing chips; distributed power generation; fast Fourier transforms; invertors; low-pass filters; notch filters; phase locked loops; power generation control; power grids; power system harmonics; synchronisation; voltage control; DER; FFT-PLL; LPN-PLL control strategy; TMS320F28335 digital signal processor; adaptive low-pass notch filter; d-q-axis transformation; distributed energy resources; fast Fourier transform concept; grid code requirement; grid phase angle detection; grid synchronization PLL method; grid voltage pollution; grid-connected PCS; harmonics; imbalance; low-voltage ride-through operation; phase-locked loop; power 10 kW; power ratings; proportional-integral controller; three-phase grid-connected inverter; Equations; Harmonic analysis; Mathematical model; Phase estimation; Phase locked loops; Power harmonic filters; Voltage fluctuations; Digital signal processor (DSP); distributed energy resources (DERs); grid code; low-pass notch (LPN) filter; phase-locked loop (PLL);
  • fLanguage
    English
  • Journal_Title
    Industrial Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0046
  • Type

    jour

  • DOI
    10.1109/TIE.2013.2245622
  • Filename
    6451253