DocumentCode
466442
Title
Cutting across layers of abstraction:: removing obstacles from the advancement of embedded systems
Author
Flautner, Krisztián
Author_Institution
ARM Ltd.
fYear
2006
fDate
22-25 Oct. 2006
Firstpage
265
Lastpage
265
Abstract
Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with steady improvements of performance and power consumption at each technology generation. This steady progress has created a sense of entitlement for the riches that future process generations would bring. Today, however, classical process scaling seems to be dead and living up to technology expectations requires continuous innovation at many levels, which comes at steadily progressing implementation and design costs. Solutions to problems need to cut across layers of abstractions and require coordination between software, architecture and circuit features. Heterogeneous multiprocessor clusters are increasingly used to deliver the required compute power for high-end applications. Heterogeneity ensures that the necessary processing power can be delivered at high levels of efficiency at reasonable implementation cost, while the use of processors endow these systems with large degrees of flexibility. One of the key challenges with these systems is system-level programming. Traditional compiler technologies are strong at programming individual cores but leave the task of parallelization to a team of experts. The first part of this talk will describe the coupling of the compiler to the system architecture on a multi-core signal-processing cluster and illustrate how compiler technology can enable the writing of portable parallel programs for it using little more than C. As claimed above, close coupling of abstraction layers can be beneficial. This can also be illustrated at the microarchitecture - circuit boundary. The second part of the talk will describe a prototype microarchitecture which is designed explicitly to deal with issues such as silicon variation and soft errors. These features in return enable system designers to focus on the typical-case performance of their implementations without having to be over-constrained by worst-case conditions.
Keywords
embedded systems; multiprocessing systems; parallel programming; parallelising compilers; signal processing; abstraction layer; compiler technology; embedded system; microarchitecture-circuit boundary; multicore signal processing cluster; portable parallel program; prototype microarchitecture; silicon technology; silicon variation; soft error; system architecture; Circuits; Computer architecture; Costs; Embedded system; Energy consumption; Microarchitecture; Power generation; Program processors; Silicon; Technological innovation; embedded systems; low power; signal processing; typical-case operation;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis, 2006. CODES+ISSS '06. Proceedings of the 4th International Conference
Conference_Location
Seoul
Print_ISBN
1-59593-370-0
Electronic_ISBN
1-59593-370-0
Type
conf
DOI
10.1145/1176254.1176318
Filename
4278526
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