• DocumentCode
    46688
  • Title

    Heterogeneous NoC Router Architecture

  • Author

    Ben-Itzhak, Yaniv ; Cidon, Israel ; Kolodny, Avinoam ; Shabun, Michael ; Shmuel, Nir

  • Author_Institution
    Electr. Eng. Dept., Technion - Israel Inst. of Technol., Haifa, Israel
  • Volume
    26
  • Issue
    9
  • fYear
    2015
  • fDate
    Sept. 1 2015
  • Firstpage
    2479
  • Lastpage
    2492
  • Abstract
    We introduce a novel heterogeneous NoC router architecture, supporting different link bandwidths and different number of virtual channels (VCs) per unidirectional port. The NoC router is based on shared-buffer architecture and has the advantages of ingress and egress bandwidth decoupling, and better performance as compared with input-buffer router architecture. We present the challenges facing the design of such heterogeneous NoC router, and describe how this router architecture addresses them. We introduce and formally prove a novel approach that reduces the number of required middle shared-buffers without affecting the performance of the router. In comparison with an optimal input-buffer homogeneous router, our NoC router improves saturation throughput by 6-47 percent for standard traffic patterns. The router achieves significant run-time improvement for NoC-based CMP running PARSEC benchmarks. It offers better scalability, area, and power reduction of 15-60 percent, for NoC based CMPs of size 4 × 4 up to 16 × 16, as compared with optimal input-buffer homogeneous and heterogeneous routers.
  • Keywords
    benchmark testing; buffer circuits; integrated circuit design; microprocessor chips; multiprocessor interconnection networks; network routing; network-on-chip; NoC-based CMP; PARSEC benchmarks; egress bandwidth decoupling; heterogeneous NoC router architecture; ingress bandwidth decoupling; link bandwidths; networks-on-chip; power reduction; run-time improvement; saturation throughput improvement; shared-buffer architecture; standard traffic patterns; virtual channels-per-unidirectional port; Bandwidth; Clocks; Electrical engineering; Memory management; Random access memory; Throughput; Interconnection architectures; network connectivity chips; routers;
  • fLanguage
    English
  • Journal_Title
    Parallel and Distributed Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1045-9219
  • Type

    jour

  • DOI
    10.1109/TPDS.2014.2351816
  • Filename
    6883223