An INL Yield Model of the Digital-to-Analog Converter

The integral nonlinearity (INL) yield of any arbitrarily segmented digital-to-analog converter (DAC) has not been accurately modeled and requires long simulation time. This paper proposes an intuitive formulation of the INL yield that leads to a simple and accurate relation between the variation of the unit source element and the DAC yield with only a few fitting parameters. These parameters can be determined for varying number of bits and varying DAC segmentation. A table of parameters is provided that can be directly applied to determine the yield without additional simulation. The validity of the model and parameters is demonstrated for measured current distributions from a current-steering DAC fabricated in a 90-nm CMOS technology.