A novel improved combined Dynamic Voltage Restorer (DVR) using Fault Current Limiter (FCL) structure

The dynamic voltage restorer (DVR) as a means of series compensation for mitigating the effect of voltage sags has been established as a preferred approach for improving power quality at sensitive load locations. In this paper a novel structure for voltage sags mitigation and for power quality improvement are proposed. Considering this fact that for rejection of high order harmonics we have to use DVRs with high-speed switches, therefore increasing the rating required for energy storage device and the need to use high-speed switches in DVRs results in a considerable increasing in costs of this equipments. So in this paper a low power DVR with low-speed switches for decreasing costs are proposed. In presented structure, the combination of FCL and DVR for decreasing the requested power rating and time response of abnormal variations at DVRs are proposed. The proposed structure operation is investigated through computer simulation by using PSCAD/EMTDC.