Leakage Reduction in Sub-100nm CMOS Technologies: Bridging the Gap Between Technology, Circuit Design and Low Power Product Requirements

With the introduction of the 130nm and 90nm CMOS technology nodes leakage reduction techniques became an essential topic of circuit and system design to meet product requirements, especially in the fields of portable applications. At the same time, a diversification into CMOS technology platforms for low standby power applications, so-called generic CMOS platforms, and high performance CMOS technologies for high-speed microprocessors is observed.