A New Fast Architecture for HD H.264 CAVLC Multi-syntax Decoder and its FPGA Implementation

In this paper, we present a fast architecture of real-time CAVLC decoder (CAVLD) implemented in a FPGA. The real-time performance is achieved by exploring the pipelining possibilities between the sub-modules and multi syntax decoding. The implemented fast CAVLD architecture, when integrated with H264 decoder was capable of parsing at 30fps for 1080p streams for an encoded bit stream at a bit rate of 200 Mbps to achieve the real-time performance, while the clock is operated at 74.25 MHz. The result numbers of ALUs are 3266 and the critical path is within 10.5ns