Charge integrating ASIC with pixel level A/D conversion

Author

Lambropoulos, C.P. ; Zervakis, E.G. ; Loukas, D.

Author_Institution

Inst. of Halkis, Evia

Volume

1

fYear

2007

fDate

Oct. 26 2007-Nov. 3 2007

Firstpage

357

Lastpage

359

Abstract

A readout architecture appropriate for X-ray imaging using charge integration has been designed. Each pixel consists of a capacitive transimpedance amplifier, a sample and hold circuit a comparator and an 8 bit DRAM. Pixel level A/D conversion and local storage of the digitized signal is performed. The target sensors are 100 um x 100 um CdTe pixel detectors and integration time of 1 ms or less can be achieved. Special measures have been taken to minimize the gain fixed pattern noise and the reset noise, while purely digital correlation double sampling can be performed.

Keywords

application specific integrated circuits; nuclear electronics; position sensitive particle detectors; readout electronics; semiconductor counters; A-D conversion; CdTe pixel detectors; DRAM; X-ray imaging; capacitive transimpedance amplifier; charge integrating ASIC; digital correlation double sampling; gain fixed pattern noise; reset noise; size 100 mum; Application specific integrated circuits; Detectors; Gain measurement; Integrated circuit measurements; Noise measurement; Performance evaluation; Performance gain; Random access memory; Sampling methods; X-ray imaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium Conference Record, 2007. NSS '07. IEEE

Conference_Location

Honolulu, HI

ISSN

1095-7863

Print_ISBN

978-1-4244-0922-8

Electronic_ISBN

1095-7863

Type

conf

DOI

10.1109/NSSMIC.2007.4436348

Filename

4436348